Yier Jin

ECE, Univ. of Florida

Yier Jin (S’07-M’12-SM’19) is the Endowed IoT Term Professor in the Warren B. Nelms Institute for the Connected World and also an Associate Professor in the Department of Electrical and Computer Engineering (ECE) in the University of Florida (UF). Prior to joining UF, he was an assistant professor in the ECE Department at the University of Central Florida (UCF). He received his PhD degree in Electrical Engineering in 2012 from Yale University after he got the B.S. and M.S. degrees in Electrical Engineering from Zhejiang University, China, in 2005 and 2007, respectively. His research focuses on the areas of embedded systems design and security, trusted hardware intellectual property (IP) cores and hardware-software co-design for modern computing systems. He is also interested in artificial intelligence (AI) security and its applications in hardware domain. His is currently focusing on the design and security analysis on Internet of Things (IoT) and wearable devices with particular emphasis on information integrity and privacy protection in the IoT era. Dr. Jin received Young Investigator Grant from Southeastern Center for Electrical Engineering Education (SCEEE) in 2015, early CAREER award from Department of Energy (DoE) in 2016, Outstanding New Faculty Award (ONFA) from ACM's Special Interest Group on Design Automation (SIGDA) in 2017, and Young Investigator Award (YIP) from Office of Naval Research (ONR) in 2019. He also received the Best Paper Award of the 52nd Design Automation Conference (DAC) in 2015, the 21st Asia and South Pacific Design Automation Conference (ASP-DAC) in 2016, the 10th IEEE Symposium on Hardware-Oriented Security and Trust (HOST) in 2017, the 2018 ACM Transactions on Design Automation of Electronic Systems (TODAES), the 28th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI) in 2018, and the Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2019. He is the IEEE Council on Electronic Design Automation (CEDA) Distinguished Lecturer. He is also a senior member of IEEE.

Talk 1

Keys to Hardware Security

Brandon Wang

Vice President, Synopsys Inc.

Brandon Wang is a Vice President at Synopsys, overseeing growth strategy for EDA products, including M&A, business and academic partnerships and other strategic initiatives. Prior to that, he served various senior management roles at Cadence and Arm in chief strategy office, marketing, solution engineering and R&D. An Electrical and Computer Engineer by training, Brandon holds 10 patents, and has published at 20+ IEEE conferences, in journal papers and invited talks; He also has an MBA degree from the Wharton School at the University of Pennsylvania.

Talk 2

Automated Implementation of Secure Silicon

Design, fabrication, assembly, test, and debug of integrated circuits and systems have become distributed across the globe, raising major concerns about their security and trustworthiness. Further, increased complexity and functionality of system-on-chips (SoCs) has resulted in increased attack surfaces and vulnerabilities. Such systems are prevalent is many critical-mission infrastructures, in which they require long and secure lifecycle. In this talk, we will provide a high-level overview of the newly funded DARPA program called AISS, with focus on RTL level security assessment of SoC designs, SoC security verification, development of security IPs, and establishing security engines to provide an end-to-end security throughout SoC lifecycle.

Mark M. Tehranipoor

Director, Florida Institute for Cybersecurity Research, Univ. of Florida

Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is also currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. His current research interests include: hardware security and trust, supply chain risk management and security, counterfeit electronics detection and prevention and reliable circuit design. Dr. Tehranipoor has published over 500 journal articles and refereed conference papers and has given more than 200 invited talks and keynote addresses. He has 8 patents, and has published 11 books and 22 book chapters. He is a recipient of 13 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 MURI award. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Avago, Mentor Graphics, R3Logic, Cisco, Qualcomm, Raytheon, MediaTeck, etc.) and Government (NSF, ARO, MDA, DOD, AFOSR, DOE, AFRL, DARPA, Draper, etc.). He serves on the program committee of more than a dozen leading conferences and workshops. He served as Program and General Chairs of several leading conferences and workshops. He co-founded a new symposium called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair (http://www.hostsymposium.org/). He is currently serving as HOST’s Chair of Steering Committee. He is also the co-founder of Trust-Hub (www.trust-hub.org) and Asian HOST (http://asianhost.org/2017/). He serves as co-EIC for newly established Journal on Hardware and Systems Security (HaSS). He also served as an Associate EIC for IEEE Design & Test, an IEEE Distinguished Speaker, and an ACM Distinguished Speaker from 2010 to 2014. He is currently serving as an Associate Editor for JETTA, JOLPE, Transactions on VLSI (TVLSI), and Transactions on Design Automation for Electronic Systems (TODAES). He served as IEEE Ambassador on Cybersecurity from 2017. Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Dr. Tehranipoor is a Fellow of IEEE, a Golden Core Member of the IEEE, and Member of ACM and ACM SIGDA.

Talk 3

Assessment of Hardware Security and Trust

Design and test are arguably the two most important phases to deliver any system. The recent DARPA AISS Program aims to create an automated chip design flow that allows security to scale consistently with other design metrics such as area, delay, power, testability, and manufacturability. Many of the hardware security research and practice in the past several decades will be implemented and integrated into this platform. Like building other systems, the assessment of such automated secure silicon implementation platform is critical. In this talk, we will outline the goals and general approaches of the AISS IV&V team led by the University of Maryland. Then we will discuss the challenges in assessing security and trust of hardware design.

Qu, Gang

ECE, Univ. of Maryland

Gang Qu received his B.S. and M.S. in mathematics from the University of Science and Technology of China (USTC) and Ph.D. in computer science in the University of California, Los Angeles (UCLA). He is currently a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park, where he leads the Maryland Embedded Systems and Hardware Security Lab (MeshSec) and the Wireless Sensor Laboratory. His recent research activities are on hardware security and trust, artificial intelligence, security in vehicular systems, and the Internet of Things. He is also known for his work on wireless sensor networks, low power and energy efficient embedded system design. He has chaired more than a dozen international conferences and workshops including AsianHOST, GLSVLSI, HOST, and SOCC. He is currently serving as the associated editor for TCAD, TETC, TODAES, JCST, and Integration. Dr. Qu is an enthusiastic teacher, he has taught various security courses, including a popular MOOC on Hardware Security through Coursera.

Talk 4

Enclave Computing on RISC-V: A Brighter Future for Platform Security?

The large attack surface of commodity operating systems motivated academia and industry to develop novel security architectures which provide strong protection for sensitive applications in enclaves that only require trust in the underlying hardware and minimal software components. However, the enclave architectures proposed by industry often lack important features, such as secure I/O, and assume threat models which do not cover important cross-layer attacks, such as microarchitectural attacks. Thus, recent works in academia have proposed a new line of enclave architectures with distinct features and more comprehensive threat models, many of which were developed on the open RISC-V architecture. In this paper, we present a brief overview of the RISC-V based enclave architectures proposed in academia, discuss their features, limitations and open challenges which we tackle in our current research using our security architecture CURE.

Ahmad-Reza Sadeghi

TU Darmstadt

Ahmad-Reza Sadeghi is a professor of Computer Science at the TU Darmstadt, Germany. He is the head of the Systems Security Lab at the Cybersecurity Research Center of TU Darmstadt. He is also the director of the Intel Research Institute for Collaborative Autonomous Resilient Systems (ICRICARS) at TU Darmstadt. He holds a Ph.D. in Computer Science from the University of Saarland, Germany. Prior to academia, he worked in R&D of Telecommunications enterprises, amongst others Ericsson Telecommunications. He has been continuously contributing to security and privacy research. He was Editor-In-Chief of IEEE Security and Privacy Magazine, served 5 years on the editorial board of the ACM Transactions on Information and System Security (TISSEC), and is currently on the editorial boards of ACM Books, ACM TODAES, ACM TIOT and ACM DTRAP. For his influential research on Trusted and Trustworthy Computing he received the renowned German “Karl Heinz Beckurts” award. This award honors excellent scientific achievements with high impact on industrial innovations in Germany. In 2018 Prof. Sadeghi received the ACM SIGSAC Outstanding Contributions Award for dedicated research, education, and management leadership in the security community and for pioneering contributions in content protection, mobile security and hardware-assisted security. SIGSAC is ACM’s Special Interest Group on Security, Audit and Control.